Hāʻawi ka ʻohana Spartan®-6 i nā mana hoʻohui ʻōnaehana alakaʻi me ka uku haʻahaʻa haʻahaʻa no nā noi kiʻekiʻe. Hāʻawi ka ʻohana he ʻumikumamākolu i nā densities i hoʻonui ʻia mai ka 3,840 a i ka 147,443 logic cell, me ka hapalua o ka hoʻohana ʻana i ka mana o nā ʻohana Spartan ma mua, a ʻoi aku ka wikiwiki, ʻoi aku ka hoʻopili piha. Kūkulu ʻia ma luna o ka ʻenehana kaʻina hana keleawe haʻahaʻa haʻahaʻa 45 nm e hāʻawi i ke koena maikaʻi loa o ke kumukūʻai, ka mana, a me ka hana, hāʻawi ka ʻohana Spartan-6 i kahi loiloi hou, ʻoi aku ka maikaʻi, ʻelua-kakau 6-input lookup table (LUT) a me kahi koho waiwai o nā poloka pae ʻōnaehana i kūkulu ʻia. Loaʻa kēia mau mea he 18 Kb (2 x 9 Kb) poloka RAM, ʻelua hanauna DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect Device configuration protection and AES enhanced Device configuration protection. Hāʻawi kēia mau hiʻohiʻona i kahi koho programmable haʻahaʻa haʻahaʻa i nā huahana ASIC maʻamau me ka maʻalahi o ka hoʻohana ʻana. Hāʻawi nā Spartan-6 FPGA i ka hoʻonā maikaʻi loa no nā hoʻolālā loiloi kiʻekiʻe, nā hoʻolālā DSP pili i nā mea kūʻai aku, a me nā noi i hoʻopili ʻia. ʻO Spartan-6 FPGAs ka papahana silikoni papahana no Targeted Design Platforms e hāʻawi ana i nā lako polokalamu i hoʻohui ʻia a me nā ʻāpana lako e hiki ai i nā mea hoʻolālā ke nānā aku i ka hana hou i ka wā e hoʻomaka ai kā lākou hoʻomohala ʻana.