XC6SLX25-2FTG256C FPGA – Field Programmable Gate Array ʻAʻole ʻae ka hale hana i nā kauoha no kēia huahana.
♠ wehewehe huahana
| Huahana Huahana | Waiwai Hiʻona |
| Mea hana: | Xilinx |
| Māhele Huahana: | FPGA - ʻĀpana Programmable Gate Array |
| RoHS: | Nā kikoʻī |
| moʻo: | XC6SLX25 |
| Ka helu o nā Elements Logic: | 24051 LE |
| Ka helu o nā I/Os: | 186 I/O |
| Voltage Hoʻolako - Min: | 1.14 V |
| Voltage Hoʻolako - Max: | 1.26 V |
| Mahana hana liʻiliʻi loa: | 0 C |
| ʻO ka wela hoʻohana kiʻekiʻe loa: | + 85 C |
| Ka helu ʻikepili: | - |
| Ka helu o nā mea lawe uila: | - |
| Kāila kau ʻana: | SMD/SMT |
| Pūʻolo/Mahi: | FBGA-256 |
| Brand: | Xilinx |
| Hoʻolaha ʻia ka RAM: | 229 kbit |
| Pākaʻi RAM - EBR: | 936 kbit |
| ʻO ke alapine hana kiʻekiʻe loa: | 1080 MHz |
| ʻAi ʻoluʻolu: | ʻAe |
| Ka helu o nā poloka Lahui Logic - LABs: | 1879 LAB |
| Voltage lako hana: | 1.2 V |
| ʻAno Huahana: | FPGA - ʻĀpana Programmable Gate Array |
| Ka nui o ka waihona hale hana: | 1 |
| Māhele ʻāpana: | Nā IC Logic Programmable |
| inoa kalepa: | Spartan |
| Huina Wehe: | 21.576 g |
♠ Spartan-6 Nānā ʻOhana
Hāʻawi ka ʻohana Spartan®-6 i nā mana hoʻohui ʻōnaehana alakaʻi me ka uku haʻahaʻa haʻahaʻa no nā noi kiʻekiʻe. Hāʻawi ka ʻohana he ʻumikumamākolu i nā densities i hoʻonui ʻia mai ka 3,840 a i ka 147,443 logic cell, me ka hapalua o ka hoʻohana ʻana i ka mana o nā ʻohana Spartan ma mua, a ʻoi aku ka wikiwiki, ʻoi aku ka hoʻopili piha. Kūkulu ʻia ma luna o kahi ʻenehana kaʻina hana keleawe haʻahaʻa haʻahaʻa 45 nm e hāʻawi i ke koena maikaʻi loa o ke kumukūʻai, ka mana, a me ka hana, hāʻawi ka ʻohana Spartan-6 i kahi loiloi hou, ʻoi aku ka maikaʻi, ʻelua papa inoa 6-input look-up table (LUT) a me kahi koho waiwai o nā poloka pae ʻōnaehana i kūkulu ʻia. Loaʻa kēia mau mea he 18 Kb (2 x 9 Kb) poloka RAM, nā ʻāpana DSP48A1 lua o ka hanauna, nā mea hoʻomanaʻo SDRAM, nā poloka hoʻokele uʻi hui pū ʻia, ka ʻenehana SelectIO™, nā poloka transceiver serial kiʻekiʻe kiʻekiʻe i hoʻopaʻa ʻia i ka mana, nā poloka Endpoint kūpono ʻo PCI Express®, nā ʻano hoʻokele mana o ka ʻōnaehana pae kiʻekiʻe, nā koho hoʻonohonoho hoʻonohonoho AES a me nā koho palekana IP hoʻonui ʻia. Hāʻawi kēia mau hiʻohiʻona i kahi koho programmable haʻahaʻa haʻahaʻa i nā huahana ASIC maʻamau me ka maʻalahi o ka hoʻohana ʻana. Hāʻawi nā Spartan-6 FPGA i ka hoʻonā maikaʻi loa no nā hoʻolālā loiloi kiʻekiʻe, nā hoʻolālā DSP pili i nā mea kūʻai aku, a me nā noi i hoʻopili ʻia. ʻO Spartan-6 FPGAs ka papahana silikoni papahana no Targeted Design Platforms e hāʻawi ana i nā lako polokalamu i hoʻohui ʻia a me nā ʻāpana lako e hiki ai i nā mea hoʻolālā ke nānā aku i ka hana hou i ka wā e hoʻomaka ai kā lākou hoʻomohala ʻana.
• ʻOhana Spartan-6:
• Spartan-6 LX FPGA: Hoʻoponopono maikaʻi ʻia
• Spartan-6 LXT FPGA: Hoʻohui serial kiʻekiʻe
• Hoʻolālā ʻia no ke kumu kūʻai haʻahaʻa
• He nui nā poloka i hoʻohui maikaʻi ʻia
• Koho maikaʻi ʻia o nā kūlana I/O
• ʻO nā pāpaʻi paʻa
• Nā pūʻolo i hoʻopaʻa ʻia i ka uwea kiʻekiʻe
• Haʻahaʻa static a me ka mana ikaika
• 45 nm kaʻina hana optimized no ke kumu kūʻai a me ka mana haʻahaʻa
• Hoʻohaʻahaʻa i ke ʻano hibernate no ka mana ʻole
• Mālama ke ʻano hoʻokuʻu i ka mokuʻāina a me ka hoʻonohonoho ʻana me ka multi-pin wake-up, hoʻonui mana
• Ka mana haʻahaʻa 1.0V kumu uila (LX FPGA, -1L wale nō)
• Kiʻekiʻe hana 1.2V core voltage (LX a me LXT FPGA, -2, -3, a me -3N māka māmā)
• Multi-voltage, multi-standard SelectIO™ interface banks
• A hiki i ka 1,080 Mb/s ka helu hoʻoili ʻikepili no kēlā me kēia ʻokoʻa I/O
• Hiki ke koho 'ia ka pahu puka, a hiki i ka 24 mA no ka pine
• 3.3V i ka 1.2VI / O nā kūlana a me nā protocols
• HSTL kumu kūʻai haʻahaʻa a me SSTL pili hoʻomanaʻo
• Hoʻokō hoʻololi wela
• I/O hiki ke ho'ololi 'ia no ka ho'omaika'i 'ana i ka pono o ka hō'ailona
• Nā transceivers serial GTP kiʻekiʻe ma nā FPGA LXT
• A hiki i 3.2 Gb/s
• Kiʻekiʻe-wikiwiki interface me: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, a me XAUI
• Poloka Endpoint i hoʻohui ʻia no nā hoʻolālā PCI Express (LXT)
• Kākoʻo ʻenehana PCI® haʻahaʻa haʻahaʻa me ka 33 MHz, 32- a me 64-bit kikoʻī.
• Nā ʻāpana DSP48A1 maikaʻi
• Ka helu helu a me ka hana hōʻailona kiʻekiʻe
• Ka wikiwiki 18 x 18 multiplier a me 48-bit accumulator
• hiki i ka paipu a me ka cascade
• Pre-adder e kōkua i ka noi kānana
• Nā poloka hoʻoponopono hoʻomanaʻo hoʻohui
• kākoʻo DDR, DDR2, DDR3, a me LPDDR
• Ka nui o ka ʻikepili a hiki i ka 800 Mb/s (12.8 Gb/s peak bandwidth)
• Hoʻolālā kaʻa kaʻa awa nui me FIFO kūʻokoʻa e hōʻemi i nā pilikia manawa hoʻolālā
• Nui nā kumu waiwai noʻonoʻo me ka hoʻonui ʻana i ka mana noʻonoʻo
• Kākau hoʻololi koho a i ʻole kākoʻo RAM i hāʻawi ʻia
• Hoʻonui maikaʻi nā LUT 6-input i ka hana a hoʻemi i ka mana
• LUT me ʻelua pāpaʻi paʻa no ka hoʻohana ʻana i ka pipeline centric
• Block RAM me ka laulā o ka granularity
• Hoʻopaʻa wikiwiki i ka RAM me ka hiki ke kākau paʻa
• 18 Kb poloka i hiki ke koho ʻia e like me ʻelua kūʻokoʻa 9 Kb poloka RAM
• Clock Management Tile (CMT) no ka hoʻonui i ka hana
• Haʻahaʻa haʻahaʻa, hikiwawe ka wati
• Hoʻopau nā Manakia Uaki Kikohoʻe (DCMs) i ka skew uaki a me ka distortion pōʻai hana
• Nā Loop Phase-Locked (PLLs) no ka uʻi haʻahaʻa
• Hoʻohui pinepine me ka hoʻonui like ʻana, ka mahele, a me ka neʻe ʻana o ka pae
• He ʻumikūmāono mau pūnaewele uaki honua haʻahaʻa haʻahaʻa
• Hoʻonohonoho maʻalahi, kākoʻo i nā kūlana haʻahaʻa
• 2-pin hoʻonohonoho ʻike ʻakomi
• SPI ākea ʻekolu ʻaoʻao (a hiki i x4) a me NOR flash kākoʻo
• Hōʻike i ka Xilinx Platform Flash me JTAG
• Kākoʻo MultiBoot no ka hoʻonui mamao me nā bitstreams he nui, me ka hoʻohana ʻana i ka pale kiaʻi
• Hoʻonui i ka palekana no ka pale hoʻolālā
• Mea hōʻike DNA no ka hōʻoia hoʻolālā
• AES bitstream encryption i nā mea ʻoi aku ka nui
• ʻOi aku ka wikiwiki o ka hoʻopili ʻana me ka hoʻonui ʻia, ke kumu kūʻai haʻahaʻa, MicroBlaze™ soft processor
• IP alakaʻi ʻoihana a me nā hoʻolālā kuhikuhi
