SPC5644AF0MLU2 32-bit Microcontrollers – MCU 32BIT3MB Flsh192KRAM
♠ wehewehe huahana
| Huahana Huahana | Waiwai Hiʻona |
| Mea hana: | NXP |
| Māhele Huahana: | 32-bit Microcontrollers - MCU |
| RoHS: | Nā kikoʻī |
| moʻo: | MPC5644A |
| Kāila kau ʻana: | SMD/SMT |
| kumu: | e200z4 |
| Ka nui o ka hoʻomanaʻo papahana: | 4 MB |
| Nui ʻikepili RAM: | 192 kB |
| ʻIkepili kaʻaahi laula: | 32 bit |
| Ka nui o ka uaki: | 120 MHz |
| Mahana hana liʻiliʻi loa: | - 40 C |
| ʻO ka wela hoʻohana kiʻekiʻe loa: | + 125 C |
| Kupono: | AEC-Q100 |
| Packaging: | pā |
| Brand: | NXP Semiconductors |
| ʻAi ʻoluʻolu: | ʻAe |
| Pūʻina hana: | MPC5644A |
| ʻAno Huahana: | 32-bit Microcontrollers - MCU |
| Ka nui o ka waihona hale hana: | 200 |
| Māhele ʻāpana: | Nā Microcontrollers - MCU |
| Māhele # Aliases: | 935321662557 |
| Huina Wehe: | 1.868 g |
♠ 32-bit Microcontrollers - MCU
Hoʻokumu ʻia ka ʻenehana hoʻokele host e200z4 microcontroller ma luna o ka ʻenehana Power Architecture® a hoʻolālā ʻia no nā noi i hoʻopili ʻia. Ma waho aʻe o ka ʻenehana Power Architecture, kākoʻo kēia kumu i nā ʻōlelo aʻoaʻo no ka hana hōʻailona kikohoʻe (DSP). Loaʻa i ka MPC5644A ʻelua pae o ka hierarchy hoʻomanaʻo me 8 KB o ka cache aʻoaʻo, kākoʻo ʻia e 192 KB ma-chip SRAM a me 4 MB o ka hoʻomanaʻo uila kūloko.
Aia ka MPC5644A i kahi kaʻa kaʻa waho, a me kahi kaʻa calibration hiki ke loaʻa wale i ka wā e hoʻohana ai i ka Freescale VertiCal Calibration System. Hōʻike kēia palapala i nā hiʻohiʻona o ka MPC5644A a hōʻike i nā hiʻohiʻona nui o ka uila a me ke kino o ka mea.
• 150 MHz e200z4 Power Architecture kumu
— Hoʻopāpā aʻo lōʻihi like ʻole (VLE)
- Hoʻolālā Superscalar me 2 mau ʻāpana hoʻokō
— A hiki i ka 2 integer a i ʻole nā kuhikuhi kiko lana no kēlā me kēia pōʻai
- A hiki i ka 4 hoʻonui a hōʻiliʻili i nā hana i kēlā me kēia pōʻai
• Hui hoʻomanaʻo
- 4 MB me ka hoʻomanaʻo ʻana i ka uila me ka ECC a me ka heluhelu ʻana i ke kākau ʻana (RWW)
— 192 KB on-chip SRAM me ka hoʻohana ʻana (32 KB) a me ECC
— 8 KB aʻo cache (me ka laka laina), hiki ke hoʻonohonoho ʻia e like me 2- a i ʻole 4-ala
- 14 + 3 KB code eTPU a me ka RAM data
— 5 ✖ 4 kuapo kea (XBAR)
— 24-komo MMU
- Ke kaʻa kaʻa waho (EBI) me ke kauā a me ke awa kumu
• Hoʻopale Palekana
— 16-komo hoʻopalekana hoʻomanaʻo (MPU)
— ʻĀpana CRC me 3 sub-modules
— ʻIke wela hui
• Keakea
— Mea hoʻoponopono hoʻopalekana hiki ke hoʻonohonoho ʻia (me NMI)
— 64-kanani DMA
• Nā kaha laina
— 3 ✖ eSCI
— 3 ✖ DSPI (2 o ia mea e kākoʻo ana i ke kahawai Micro Second Channel [MSC])
— 3 ✖ FlexCAN me 64 mau memo i kēlā me kēia
— 1 ✖ FlexRay module (V2.1) a hiki i ka 10 Mbit/s me ʻelua a i ʻole hoʻokahi alahele a me 128 mau mea memo a me ECC
• 1 ✖ eMIOS: 24 mau kaha hui
• 1 ✖ eTPU2 (eTPU hanauna lua)
— 32 mau kaha maʻamau
— 1 ✖ module pane (6 nā kaha me ʻekolu mau puka no kēlā me kēia kanal)
• 2 mea hoʻololi analog-to-digital i hoʻonui ʻia (eQADC)
— He kanaha 12-bit mau ala komo (nui ma 2 ADCs); hiki ke hoʻonui ʻia i nā kaha 56 me nā multiplexers waho
— 6 laina kauoha
- Kākoʻo Trigger a me DMA
— 688 ns manawa hoʻololi liʻiliʻi
• ʻO ka mea hoʻouka ʻo CAN/SCI/FlexRay Bootstrap me ka Boot Assist Module (BAM)
• Nexus
— Papa 3+ no ke kumu e200z4
— Papa 1 no ka eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS)
- Ka inoa o nā semaphore (32-bits) a me kahi papa inoa ʻike
- Hoʻohana ʻia ma ke ʻano he ʻāpana o ka protocol acquisition data triggered
— Hoʻohana ʻia ka pine EVTO e kamaʻilio me ka mea hana waho
• Hanau uaki
— ʻO ka oscillator nui ma ka chip 4–40 MHz
— On-chip FMPLL (frequency-modulated phase-lock loop)
• A hiki i 120 laina I/O kumu nui
— Hiki ke hoʻolālā ʻia e like me ka hoʻokomo, ka hoʻopuka a i ʻole ka hana kūikawā
— Paepae hiki ke hoʻolālā (hysteresis)
• Ke ano hoemi mana: lohi, ku a me ke ku ana
• Hoʻolālā lako lako
— 5 V lako hoʻokahi me ka ballast waho
— Nui nā lako waho: 5 V, 3.3 V a me 1.2 V
• Nā pūʻolo
— 176 LQFP
— 208 MAPBGA
— 324 TEPBGA
496-pin CSP (mea hana calibration wale nō)
